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1 for more information www.linear.com/LTM2173-14 lt m2173 -14 typical application features applications description 14- bit, 80msps low power quad adc lt m2173 -14, 80msps , 2- tone fft, f in = 70mhz and 75mhz the ltm ? 2173- 14 is a 4- channel, simultaneous sam - pling 14- bit a/d converter designed for digitizing high frequency, wide dynamic range signals. ac performance includes 73db snr and 88db spurious free dynamic range (sfdr). low power consumption per channel reduces heat in high channel count applications. integrated bypass capacitance and flow-through pinout reduces overall board space requirements. dc specs include 1lsb inl (typ), 0.3lsb dnl (typ) and no missing codes over temperature. the transition noise is a low 1.2lsb rms . the digital outputs are serial lvds to minimize the num - ber of data lines. each channel outputs two bits at a time ( 2- l an e mode). at lower sampling rates there is a one bit per channel option ( 1- lane mode). the enc + and enc C inputs may be driven differentially or single-ended with a sine wave, pecl, lvds, ttl, or cmos inputs. an internal clock duty cycle stabilizer al- lows high performance at full speed for a wide range of clock duty cycles. n 4- channel simultaneous sampling adc n 73db snr n 88db sfdr n low power : 96mw per channel n single 1.8v supply n serial lvds outputs : 1 or 2 bits per channel n selectable input ranges: 1v p-p to 2v p-p n 800mhz full power bandwidth s/h n shutdown and nap modes n serial spi port for configuration n internal bypass capacitance, no external components n 140- pin ( 11.25mm 9mm ) bga package n automotive n communications n cellular base stations n software defined radios n portable medical imaging n multichannel data acquisition n nondestructive testing all registered trademarks and trademarks are the property of their respective owners. 1 11 12 7 3 4 2 1 1 2 3 4 217314 1 data serializer encode input serialized lvds outputs 1.8v v dd 1.8v ov dd out1a out1b out2a out2b out4a out4b data clock out frame gnd gnd 217314 ta01 s/h channel 1 analog input 14-bit adc core s/h channel 2 analog input 14-bit adc core s/h channel 4 analog input 14-bit adc core pll ? ? ? ? ? ? ? ? ? ? ? ? 217314f
2 for more information www.linear.com/LTM2173-14 lt m2173 -14 http : //www.linear.com/product/ lt m2173 -14#orderinfo absolute maximum ratings (notes 1, 2) pin configuration order information lead free finish tray part marking* package description temperature range lt m2173 hy-14#pbf lt m2173 hy-14#pbf lt m2173 y14 140- lead ( 11.25mm 9mm 2.72mm ) bga C 40 c to 105 c ? de vice temperature grade is indicated by a label on the shipping container. ? pa d or ball finish code is per ipc/jedec j-std-609. ? te rminal finish part marking : www.linear.com/leadfree ? th is product is not recommended for second side reflow. for more information, go to www.linear.com/bga-assy ? re commended bga pcb assembly and manufacturing procedures: www.linear.com/umodule/pcbsssembly ? bg a package and tray drawings: www.linear.com/packaging ? th is product is moisture sensitive. for more information, go to: www.linear.com/bga-assy supply voltages v dd , ov dd ................................................ C 0.3 v to 2v analog input voltage (a in + , a in C , par/ ser , sense) (note 3) .......... C 0. 3v to (v dd + 0.2v ) digital input voltage (enc + , enc C , cs , sdi, sck) (note 4) .................................... C 0. 3v to 3.9v sdo (note 4) ............................................. C 0. 3v to 3.9v digital output voltage ................ C 0. 3v to (ov dd + 0.3v ) operating temperature range lt m2 173 ............................................ C 40 c to 105 c storage temperature range .................. C 55 c to 125 c 1 17432 14 112 272 t jmax = 150 c, ja = 30 c /w, jc = 25 c /w, jb = 15 c /w, jc bottom = 12 c /w 217314f
3 for more information www.linear.com/LTM2173-14 lt m2173 -14 converter characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) parameter conditions lt m2173 -14 units min typ max resolution (no missing codes) l 14 bits integral linearity error differential analog input (note 6) l C 2.75 1 2.75 lsb differential linearity error differential analog input l C 0.8 0.3 0.8 lsb offset error (note 7) l C 12 3 12 mv gain error internal reference external reference l C 2 .6 C 1. 3 C 1.3 0 %fs %f s of fset drift 20 v/ c full-scale drift internal reference external reference 35 25 p pm / c ppm/ c gai n matching external reference 0.2 %fs offset matching 3 mv transition noise external reference 1.2 lsb rms analog input the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units v in analog input range (a in + C a in C ) 1.7v < v dd < 1.9v l 1 to 2 v p-p v in(cm) analog input common mode (a in + + a in C )/2 differential analog input (note 8) l v cm C 100mv v cm v cm + 100mv v v sense external voltage reference applied to sense external reference mode l 0.625 1.250 1.300 v i incm analog input common mode current per pin, 80msps 100 a i i n1 analog input leakage current 0 < a in + , a in C < v dd , no encode l C1 1 a i i n2 par/ ser input leakage current 0 < par/ ser < v dd l C3 3 a i i n3 sense input leakage current 0.625 < sense < 1.3v l C6 6 a t ap sample-and-hold acquisition delay time 0 ns t jitter sample-and-hold acquisition delay jitter 0.15 ps rms cmrr analog input common mode rejection ratio 80 db bw-3b full-power bandwidth figure 6 test circuit 800 mhz 217314f
4 for more information www.linear.com/LTM2173-14 lt m2173 -14 dynamic accuracy the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = C 1dbfs . (note 5) symbol parameter conditions lt m2173 -14 units min typ max snr signal-to-noise ratio 5mhz input 70mhz input 14 0mhz in put l 69.7 73 72.9 72.5 db f s dbfs dbfs sf dr spurious free dynamic range 2nd or 3rd harmonic 5mh z input 70mhz input 14 0mhz in put l 74 88 85 82 db f s dbfs dbfs sp urious free dynamic range 4th harmonic or higher 5mh z input 70mhz input 14 0mhz in put l 82 90 90 90 db f s dbfs dbfs s/ (n+d) signal-to-noise plus distortion ratio 5mhz input 70mhz input 14 0mhz in put l 69.6 7 2.9 7 2.6 72 db f s dbfs dbfs cr osstalk, near channel 10mhz input (note 12) C 90 dbc crosstalk, far channel 10mhz input (note 12) C 105 dbc internal reference characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. a in = C 1dbfs . (note 5) parameter conditions min typ max units v cm output voltage i out = 0 0.5 ? v dd C 25mv 0.5 ? v dd 0.5 ? v dd + 25mv v v cm output temperature drift 25 ppm/ c v cm output resistance C 600a < i out < 1ma 4 v ref output voltage i out = 0 1.225 1.250 1.275 v v ref output temperature drift 25 ppm/ c v ref output resistance C 400a < i out < 1ma 7 v ref line regulation 1.7v < v dd < 1.9v 0.6 mv/v 217314f
5 for more information www.linear.com/LTM2173-14 lt m2173 -14 digital inputs and outputs the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions min typ max units encode inputs (enc + , enc C ) v id differential input voltage (note 8) l 0.2 v v icm common mode input voltage internally set externally set (note 8) l 1.1 1. 2 1. 6 v v v in input voltage range enc + , enc C to gnd l 0.2 3.6 v r in input resistance (see figure 10) 10 k c in input capacitance 3.5 pf digital inputs ( cs , sdi, sck in serial or parallel programming mode. sdo in parallel programming mode) v ih high level input voltage v dd = 1.8v l 1.3 v v il low level input voltage v dd = 1.8v l 0.6 v i in input current v in = 0v to 3.6v l C 10 10 a c in input capacitance 3 pf sdo output (serial programming mode. open-drain output. requires 2k pull-up resistor if sdo is used) r ol logic low output resistance to gnd v dd = 1.8v , sdo = 0v 200 i oh logic high output leakage current sdo = 0v to 3.6v l C 10 10 a c out output capacitance 3 pf digital data outputs v od differential output voltage 100 differential load, 3.5ma mode 100 d ifferential load, 1.75ma mo de l l 247 125 3 50 17 5 454 25 0 mv mv v os common mode output voltage 100 differential load, 3.5ma mode 100 d ifferential load, 1.75ma mo de l l 1.125 1.125 1. 2 50 1.250 1.3 75 1.375 v v r term on-chip termination resistance termination enabled, ov dd = 1.8v 100 217314f
6 for more information www.linear.com/LTM2173-14 lt m2173 -14 power requirements the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 9) symbol parameter conditions lt m2173 -14 units min typ max v dd analog supply voltage (note 10) l 1.7 1.8 1.9 v ov dd output supply voltage (note 10) l 1.7 1.8 1.9 v i vdd analog supply current sine wave input l 189 205 ma i ovdd digital supply current 2- lane mode, 1.75ma mode 2- l ane mode, 3.5ma mo de l l 25 47 29 52 ma ma p diss power dissipation 2- lane mode, 1.75ma mode 2- l ane mode, 3.5ma mo de l l 385 425 4 21 4 62 mw mw p sleep sleep mode power 1 mw p nap nap mode power 85 mw p diffclk power decrease with single-ended encode mode enabled (no decrease for sleep mode) 20 mw timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) symbol parameter conditions lt m2173 -14 units min typ max f s sampling frequency (notes 10,11) l 5 80 mhz t encl enc low time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 5.93 2 6. 2 5 6.25 100 10 0 ns ns t ench enc high time (note 8) duty cycle stabilizer off duty cycle stabilizer on l l 5.93 2 6. 2 5 6.25 100 10 0 ns ns t ap sample-and-hold acquisition delay time 0 ns symbol parameter conditions min typ max units digital data outputs (r term = 100 differential, c l = 2pf to gnd on each output) t ser serial data bit period 2- lanes, 16- bit serialization 2- l anes, 14- b it serialization 2- l anes, 12- b it serialization 1- l ane, 16- b it serialization 1- l ane, 14- b it serialization 1- l ane, 12- b it serialization 1/(8 ? f s ) 1/(7 ? f s ) 1/(6 ? f s ) 1/(16 ? f s ) 1/(14 ? f s ) 1/(12 ? f s ) s s s s s s t frame fr to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t data data to dco delay (note 8) l 0.35 ? t ser 0.5 ? t ser 0.65 ? t ser s t pd propagation delay (note 8) l 0.7n + 2 ? t ser 1.1n + 2 ? t ser 1.5n + 2 ? t ser s t r output rise time data, dco, fr, 20% to 80% 0.17 ns t f output fall time data, dco, fr, 20% to 80% 0.17 ns dco cycle-cycle jitter t ser = 1ns 60 ps p-p pipeline latency 6 cycles 217314f
7 for more information www.linear.com/LTM2173-14 lt m2173 -14 symbol parameter conditions min typ max units spi port timing (note 8) t sck sck period write mode read back mode, c sdo = 20pf , r pullup = 2k l l 40 250 ns ns t s cs to sck setup time l 5 ns t h sck to cs setup time l 5 ns t ds sdi setup time l 5 ns t dh sdi hold time l 5 ns t do sck falling to sdo valid read back mode, c sdo = 20pf , r pullup = 2k l 125 ns timing characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25 c. (note 5) note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd (unless otherwise noted). note 3: when these pin voltages are taken below gnd or above v dd , they will be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd or above v dd without latchup. note 4: when these pin voltages are taken below gnd they will be clamped by internal diodes. when these pin voltages are taken above v dd they will not be clamped by internal diodes. this product can handle input currents of greater than 100ma below gnd without latchup. note 5: v dd = ov dd = 1.8v , f sample = 80mhz , 2- lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. note 6: integral nonlinearity is defined as the deviation of a code from a best fit straight line to the transfer curve. the deviation is measured from the center of the quantization band. note 7: offset error is the offset voltage measured from C0.5 lsb when the output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in 2 s complement output mode. note 8: guaranteed by design, not subject to test. note 9: v dd = ov dd = 1.8v , f sample = 80mhz , 2- lane output mode, differential enc + /enc C = 2v p-p sine wave, input range = 2v p-p with differential drive, unless otherwise noted. the supply current and power dissipation specifications are totals for the entire device, not per channel. note 10 : recommended operating conditions. note 11 : the maximum sampling frequency depends on the speed grade of the part and also which serialization mode is used. the maximum serial data rate is 1000mbps so t ser must be greater than or equal to 1ns . note 12 : near-channel crosstalk refers to ch. 1 to ch.2, and ch.3 to ch.4. far-channel crosstalk refers to ch.1 to ch.3, ch.1 to ch.4, ch.2 to ch.3, and ch.2 to ch.4. 217314f
8 for more information www.linear.com/LTM2173-14 lt m2173 -14 2- lane output mode, 14- bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 sample n-3 n+1 n+2 n 217314 td02 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 d7 d5 d3 d1 d13 d11 d9 out#a ? out#a + fr ? fr + d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 d6 d4 d2 d0 d12 d10 d8 out#b ? out#b + note that in this mode fr + /fr ? has two times the period of enc + /enc ? timing diagrams 2- lane output mode, 16- bit serialization* analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 *see the digital outputs section sample n-5 sample n-4 n+1 n 217314 td01 d5 d3 d1 0 d13 d11 d9 d7 d5 d3 d1 0 d13 d11 d9 out#a ? out#a + fr ? fr + d4 d2 d0 0 d12 d10 d8 d6 d4 d2 d0 0 d12 d10 d8 out#b ? out#b + 217314f
9 for more information www.linear.com/LTM2173-14 lt m2173 -14 timing diagrams 2- lane output mode, 12- bit serialization 1- lane output mode, 16- bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t ser t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n 217314 td03 d9 d7 d5 d3 d13 d11 d9 d7 d5 d3 d13 d11 d9 out#a ? out#a + fr + fr ? d8 d6 d4 d2 d12 d10 d8 d6 d4 d2 d12 d10 d8 out#b ? out#b + analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 217314 td04 d1 d0 0 0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 0 0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 217314f
10 for more information www.linear.com/LTM2173-14 lt m2173 -14 timing diagrams 1- lane output mode, 14- bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 217314 td06 d3 d2 d1 d0 d13 d12 d11 d10 d12 d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 1- lane output mode, 12- bit serialization analog input enc ? enc + dco ? dco + t ap t ench t encl t ser t pd t data t frame sample n-6 sample n-5 sample n-4 n+1 n t ser t ser 217314 td07 d5 d4 d3 d2 d13 d12 d11 d10 d12 d11 d9 d8 d7 d6 d5 d4 d3 d2 d13 out#a ? out#a + fr ? fr + out#b + , out#b ? are disabled 217314f
11 for more information www.linear.com/LTM2173-14 lt m2173 -14 a6 t s t ds a5 a4 a3 a2 a1 a0 xx d7 d6 d5 d4 d3 d2 d1 d0 xx xx xx xx xx xx xx cs sck sdi r/w sdo high impedance spi port timing (readback mode) spi port timing (write mode) t dh t do t sck t h a6 a5 a4 a3 a2 a1 a0 d7 d6 d5 d4 d3 d2 d1 d0 217314 td08 cs sck sdi r/w sdo high impedance timing diagrams 217314f
12 for more information www.linear.com/LTM2173-14 lt m2173 -14 typical performance characteristics lt m2173 -14 : 8k point 2- tone fft, f in = 70mhz , 75mhz , C 7dbfs per tone, 80msps lt m2173 -14 : shorted input histogram lt m2173 -14 : 8k point fft, f in = 30mhz , C 1dbfs , 80msps lt m2173 -14 : 8k point fft, f in = 70mhz , C 1dbfs , 80msps lt m2173 -14 : 8k point fft, f in = 140mhz , C 1dbfs , 80msps lt m2173 -14 : integral nonlinearity (inl) lt m2173 -14 : differential nonlinearity (dnl) lt m2173 -14 : 8k point fft, f in = 5mhz , C 1dbfs , 80msps output code 0 ?1.0 ?0.4 ?0.2 ?0.6 ?0.8 dnl error (lsb) 0 0.4 0.2 0.6 0.8 1.0 4096 8192 12288 16384 217314 g02 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 217314 g03 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 217314 g04 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 217314 g05 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 217314 g06 frequency (mhz) 0 ?100 ?110 ?120 ?70 ?60 ?80 ?90 amplitude (dbfs) ?50 ?30 ?40 ?20 ?10 0 10 20 30 40 217314 g07 output code 8184 1000 0 3000 2000 count 4000 5000 6000 8186 8188 8190 8192 217314 g08 output code 0 ?2.0 ?0.5 ?1.0 ?1.5 inl error (lsb) 0 0.5 1.0 1.5 2.0 4096 8192 12288 16384 9009101114 g29 217314f
13 for more information www.linear.com/LTM2173-14 lt m2173 -14 typical performance characteristics lt m2173 -14 : i vdd vs sample rate, 5mhz sine wave input, C 1dbfs dco cycle-cycle jitter vs serial data rate lt m2173 -14 : snr vs sense, f in = 5mhz , C 1dbfs sense pin (v) 0.6 71 68 69 70 67 66 72 73 74 snr (dbfs) 0.7 0.8 0.9 1.1 1.2 1.3 1 217314 g13 lt m2173 -14 : sfdr vs input level, f in = 70mhz , 2v range, 80msps input level (dbfs) ?80 60 50 40 30 20 10 0 80 70 sfdr (dbc and dbfs) 90 100 110 ?70 ?60 ?50 ?40 ?30 ?20 ?10 0 217314 g11 dbfs dbc input frequency (mhz) 0 90 85 80 75 70 65 95 sfdr (dbfs) 50 100 150 200 250 300 350 217314 g10 lt m2173 -14 : sfdr vs input frequency, C 1dbfs , 2v range, 80msps input frequency (mhz) 0 72 71 70 69 68 67 66 74 73 snr (dbfs) 50 100 150 200 250 300 350 217314 g09 lt m2173 -14 : snr vs input frequency, C 1dbfs , 2v range, 80msps serial data rate (mbps) 350 300 250 200 150 100 50 0 peak-to-peak jitter (ps) 0 200 400 600 800 1000 217314 g14 sample rate (msps) 190 180 170 160 150 140 i vdd (ma) 0 20 40 60 80 217314 g12 217314f
14 for more information www.linear.com/LTM2173-14 lt m2173 -14 pin functions a i n1 + ( b2 ): channel 1 positive differential analog input. a i n1 C ( b1 ): channel 1 negative differential analog input. v c m12 ( b3 ): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 1 and 2. v cm is internally bypassed to ground with a 0.1f ceramic capacitor. no external capacitance is required. a i n2 + ( g2 ): channel 2 positive differential analog input. a i n2 C ( g1 ): channel 2 negative differential analog input. a i n3 + ( h1 ): channel 3 positive differential analog input. a i n3 C ( h2 ): channel 3 negative differential analog input. v c m34 ( n3 ): common mode bias output, nominally equal to v dd /2. v cm should be used to bias the common mode of the analog inputs of channels 3 and 4. v cm is internally bypassed to ground with a 0.1f ceramic capacitor. no external capacitance is required. a i n4 + ( n1 ): channel 4 positive differential analog input. a i n4 C ( n2 ): channel 4 negative differential analog input. v dd ( d3 , d4 , e3 , e4 , k3 , k4 , l3 , l4 ): 1.8v analog power supply. v dd is internally bypassed to ground with 0.1f ceramic capacitors. enc + ( p5 ): encode input. conversion starts on the rising edge. enc C ( p6 ): encode complement input. conversion starts on the falling edge. cs ( l5 ): in serial programming mode, (par/ ser = 0v ), cs is the serial interface chip select input. when cs is low, sck is enabled for shifting data on sdi into the mode control registers. in parallel programming mode (par/ ser = v dd ), cs selects 2- lane or 1- lane output mode. cs can be driven with 1.8v to 3.3v logic. sck ( l6 ): in serial programming mode, (par/ ser = 0v ), sck is the serial interface clock input. in parallel pro - gramming mode (par/ ser = v dd ), sck selects 3.5ma or 1.75ma lvds output currents. sck can be driven with 1.8v to 3.3v logic. sdi ( m6 ): in serial programming mode, (par/ ser = 0v ), sdi is the serial interface data input. data on sdi is clocked into the mode control registers on the rising edge of sck. in parallel programming mode (par/ ser = v dd ), sdi can be used to power down the part. sdi can be driven with 1.8v to 3.3v logic. gnd (see pin configuration table) : adc power ground. use multiple vias close to pins. ov dd ( g9 , g10 ): output driver supply. ov dd is internally bypassed to ground with a 0.1f ceramic capacitor. sdo ( e6 ): in serial programming mode, (par/ ser = 0v ), sdo is the optional serial interface data output. data on sdo is read back from the mode control registers and can be latched on the falling edge of sck. sdo is an open- drain n-channel mosfet output that requires an external 2k pull-up resistor from 1.8v to 3.3v . if read back from the mode control registers is not needed, the pull-up resistor is not necessary and sdo can be left unconnected. in parallel programming mode (par/ ser = v dd ), sdo is an input that enables internal 100 termination resistors on the digital outputs. when used as an input, sdo can be driven with 1.8v to 3.3v logic through a 1k series resistor. par/ ser ( a7 ): programming mode selection pin. connect to ground to enable the serial programming mode. cs , sck, sdi and sdo become a serial interface that control the a/d operating modes. connect to v dd to enable parallel programming mode where cs , sck, sdi and sdo become parallel logic inputs that control a reduced set of the a/d operating modes. par/ ser should be connected directly to ground or the v dd of the part and not be driven by a logic signal. v ref ( b6 ): reference voltage output. v ref is internally bypassed to ground with a 2.2f ceramic capacitor, nomi - nally 1.25v . sense ( c5 ): reference programming pin. connecting sense to v dd selects the internal reference and a 1v input range. connecting sense to ground selects the internal reference and a 0.5v input range. an external reference between 0.625v and 1.3v applied to sense selects an input range of 0.8 ? v sense . sense is inter - nally bypassed to ground with a 0.1f c e ramic capacitor. 217314f
15 for more information www.linear.com/LTM2173-14 lt m2173 -14 pin functions lvds outputs all pins in this section are differential lvds outputs. the output current level is programmable. there is an optional internal 100? termination resistor between the pins of each lvds output pair. out1a C /out1a + , out1b C /out1b + ( e7 / e8 , c8 / d8 ): serial data outputs for channel 1. in 1- lane output mode only out1a C /out1a + are used. out2a C /out2a + , out2b C /out2b + ( c9 / c10 , f7 / f8 ): serial data outputs for channel 2. in 1- lane output mode only out2a C /out2a + are used. out3a C /out3a + , out3b C /out3b + ( j8 / j7 , k8 / k7 ): serial data outputs for channel 3. in 1- lane output mode only out3a C /out3a + are used. out4a C /out4a + , out4b C /out4b + ( l8 / m8 , m10 / m9 ): serial data outputs for channel 4. in 1- lane output mode only out4a C /out4a + are used. fr C /fr + ( h7 / h8 ): frame start outputs. dco C /dco + ( g8 / g7 ): data clock outputs. 1 2 3 4 5 6 7 8 9 10 a gnd gnd gnd gnd gnd gnd par/ ser gnd gnd gnd b a i n1 C a i n1 + v c m12 gnd gnd v ref gnd gnd gnd gnd c gnd gnd gnd gnd sense gnd gnd out1b C out2a C out 2a + d gnd gnd v dd v dd gnd gnd gnd out1b + gnd gnd e gnd gnd v dd v dd gnd sdo out1a C out1a + gnd gnd f gnd gnd gnd gnd gnd gnd out2b C out2b + gnd gnd g a i n2 C a i n2 + gnd gnd gnd gnd dco + dco C ov dd ov dd h a i n3 + a i n3 C gnd gnd gnd gnd fr C fr + gnd gnd j gnd gnd gnd gnd gnd gnd out3a + out3a C gnd gnd k gnd gnd v dd v dd gnd gnd out3b + out3b C gnd gnd l gnd gnd v dd v dd cs sck gnd out4a C gnd gnd m gnd gnd gnd gnd gnd sdi gnd out4a + out4b + out4b C n a i n4 + a i n4 C v c m34 gnd gnd gnd gnd gnd gnd gnd p gnd gnd gnd gnd enc + enc C gnd gnd gnd gnd to p view of bga package (looking through component). pin configuration table 217314f
16 for more information www.linear.com/LTM2173-14 lt m2173 -14 functional block diagram figure 1. functional block diagram diff ref amp ref buffer refh refl range select 1.25v reference gnd v dd /2 217314 f01 sense v ref mode control registers ov dd = 1.8v v dd = 1.8v out1a + out1a ? out1b + out1b ? s/h ch 1 analog input 14-bit adc core out2a + out2a ? out2b + out2b ? s/h ch 2 analog input 14-bit adc core out3a + out3a ? out3b + out3b ? s/h ch 3 analog input 14-bit adc core out4a + out4a ? out4b + out4b ? s/h ch 4 analog input 14-bit adc core dco fr enc + enc ? sdo sdi sck cs par/ ser v cm12 v cm34 pll data serializer 217314f
17 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information converter operation the lt m2173 -14 is a low power, 4- channel, 14- bit, 80msps a/d converter that is powered by a single 1.8v supply. the analog inputs should be driven differentially. the encode input can be driven differentially for optimal jitter perfor - mance, or single-ended for lower power consumption. the digital outputs are serial lvds to minimize the num - ber of data lines. each channel outputs two bits at a time ( 2- l ane mode). at lower sampling rates there is a one bit per channel option ( 1- lane mode). many additional fea - tures can be chosen by programming the mode control registers through a serial spi port. analog input the analog inputs are differential cmos sample-and-hold circuits (figure 2). the inputs should be driven differen - tially around a common mode voltage set by the appropri - ate v cm output pins, which are nominally v dd /2. for the 2v input range, the inputs should swing from v cm C 0.5v to v cm + 0.5v . there should be 180 phase difference between the inputs. the eight channels are simultaneously sampled by a shared encode circuit (figure 2). input drive circuits input filtering if possible, there should be an rc low pass filter right at the analog inputs. this lowpass filter isolates the drive cir - cuitry from the a/d sample-and-hold switching, and also limits wideband noise from the drive circuitry. figure 3 shows an example of an input rc filter. the rc compo - nent values should be chosen based on the application s i n put frequency. transformer coupled circuits figure 3 shows the analog input being driven by an rf transformer with a center-tapped secondary. the center tap is biased with v cm , setting the a/d input at its optimal dc level. at higher input frequencies a transmission line balun transformer (figures 4 to 6) has better balance, resulting in lower a/d distortion. figure 2. equivalent input circuit. only one of the eight analog channels is shown c sample 3.5pf r on 25 r on 25 v dd v dd LTM2173-14 a in + 217314 f02 c sample 3.5pf v dd a in ? enc ? enc + 1.2v 10k 1.2v 10k c parasitic 1.8pf c parasitic 1.8pf 10 10 figure 3. analog input circuit using a transformer. recommended for input frequencies from 5mhz to 70mhz 25 25 25 25 50 0.1f a in + a in ? 12pf 0.1f v cm LTM2173-14 analog input 0.1f t1 1:1 t1: ma/com mabaes0060 resistors, capacitors are 0402 package size 217314 f03 217314f
18 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information amplifier circuits figure 7 shows the analog input being driven by a high speed differential amplifier. the output of the amplifier is ac-coupled to the a/d so the amplifier s output common mode voltage can be optimally set to minimize distortion. figure 4. recommended front end circuit for input frequencies from 70mhz to 170mhz 25 25 50 0.1f a in + a in ? 4.7pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: ma/com mabaes0060 resistors, capacitors are 0402 package size 217314 f04 LTM2173-14 25 25 50 0.1f a in + a in ? 1.8pf 0.1f v cm analog input 0.1f 0.1f t1 t2 t1: ma/com maba-007159-000000 t2: coilcraft wbc1-1lb resistors, capacitors are 0402 package size 217314 f05 LTM2173-14 25 25 50 0.1f 2.7nh 2.7nh a in + a in ? 0.1f v cm analog input 0.1f 0.1f t1 t1: ma/com etc1-1-13 resistors, capacitors are 0402 package size 217314 f06 LTM2173-14 25 25 200 200 0.1f a in + a in ? 12pf 0.1f v cm LTM2173-14 217314 f07 ? ? + + analog input high speed differential amplifier 0.1f at very high frequencies an rf gain block will often have lower distortion than a differential amplifier. if the gain block is single-ended, then a transformer circuit (figures 4 to 6) should convert the signal to differential before driving the a/d. figure 5. recommended front end circuit for input frequencies from 170mhz to 300mhz figure 6. recommended front end circuit for input frequencies above 300mhz figure 7. front end circuit using a high speed differential amplifier 217314f
19 for more information www.linear.com/LTM2173-14 lt m2173 -14 v ref 1.25v refh sense tie to v dd for 2v range; tie to gnd for 1v range; range = 1.6 ? v sense for 0.65v < v sense < 1.300v refl 2.2f internal adc high reference buffer 217314 f08 LTM2173-14 5 0.8x diff amp internal adc low reference 1.25v bandgap reference 0.625v range detect and control 2.2f 0.1f 0.1f 0.1f applications information figure 8. reference circuit figure 9. using an external 1.25v reference reference the lt m2173 -14 has an internal 1.25v voltage reference. for a 2v input range using the internal reference, connect sense to v dd . for a 1v input range using the internal reference, connect sense to ground. for a 2v input range with an external reference, apply a 1.25v reference volt - age to sense (figure 9). sense 1.25v external reference 1f 217314 f09 LTM2173-14 the input range can be adjusted by applying a voltage to sense that is between 0.625v and 1.30v . the input range will then be 1.6 ? v sense . the reference is shared by all four adc channels, so it is not possible to independently adjust the input range of individual channels. the v ref and sense pins are internally bypassed, as shown in figure 8. 217314f
20 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information encode input the signal quality of the encode inputs strongly affects th e a/d noise performance. the encode inputs should be treated as analog signals do not route them next to digital traces on the circuit board. there are two modes of operation for the encode inputs : the differential encode mode (figure 10), and the single-ended encode mode (figure 11). the differential encode mode is recommended for sinu - soidal, pecl, or lvds encode inputs (figures 12 and 13). figure 13. pecl or lvds encode drive figure 12. sinusoidal encode drive 50 100 0.1f 0.1f 0.1f t1 t1 = ma/com etc1-1-13 resistors and capacitors are 0402 package size 50 LTM2173-14 217314 f12 enc ? enc + enc + enc ? pecl or lvds clock 0.1f 0.1f 217314 f13 LTM2173-14 v dd LTM2173-14 217314 f10 enc ? enc + 15k v dd differential comparator 30k figure 10. equivalent encode input circuit for differential encode mode 30k enc + enc ? 217314 f11 0v 1.8v to 3.3v LTM2173-14 cmos logic buffer figure 11. equivalent encode input circuit for single-ended encode mode the encode inputs are internally biased to 1.2v through 10 k equivalent resistance. the encode inputs can be taken above v dd (up to 3.6v ), and the common mode range is from 1.1v to 1.6v . in the differential encode mode, enc C should stay at least 200mv above ground to avoid falsely triggering the single-ended encode mode. for good jitter performance enc + should have fast rise and fall times. the single-ended encode mode should be used with cmos encode inputs. to select this mode, enc C is con - nected to ground and enc + is driven with a square wave 217314f
21 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information encode input. enc + can be taken above v dd (up to 3.6v ) so 1.8v to 3.3v cmos logic levels can be used. the enc + threshold is 0.9v . for good jitter performance enc + should have fast rise and fall times. clock pll and duty cycle stabilizer the encode clock is multiplied by an internal phase-locked loop (pll) to generate the serial digital output data. if the encode signal changes frequency or is turned off, the pll requires 25s to lock onto the input clock. a clock duty cycle stabilizer circuit allows the duty cycle of the applied encode signal to vary from 30% to 70%. in the serial programming mode it is possible to disable the duty cycle stabilizer, but this is not recommended. in the parallel programming mode the duty cycle stabilizer is always enabled. digital outputs the digital outputs of the lt m2173 -14 are serialized lvds signals. each channel outputs two bits at a time ( 2- lane mode). at lower sampling rates there is a one bit per chan - nel option ( 1- lane mode). the data can be serialized with 16, 14, or 12- bit serialization (see the timing diagrams section for details). note that with 12- bit serialization the two lsbs are not available. the output data should be latched on the rising and falling edges of the data clock out (dco). a data frame output (fr) can be used to determine when the data from a new conversion result begins. in the 2- lane, 14- bit serialization mode, the frequency of the fr output is halved. the maximum serial data rate for the data outputs is 1gbps , so the maximum sample rate of the adc will depend on the serialization mode as well as the speed grade of the adc (see table 1). the minimum sample rate for all serialization modes is 5msps . by default the outputs are standard lvds levels : 3.5ma output current and a 1.25v output common mode volt- age. an external 100? differential termination resistor is required for each lvds output pair. the termination resistors should be located as close as possible to the lvds receiver. the outputs are powered by ov dd which is independent from the a/d core power. table 1. maximum sampling frequency for all serialization modes. serialization mode maximum sampling frequency, f s (mhz) dco frequency fr frequency serial data rate 2- lane 16- bit serialization 80 4 ? f s f s 8 ? f s 2- lane 14- bit serialization 80 3.5 ? f s 0.5 ? f s 7 ? f s 2- lane 12- bit serialization 80 3 ? f s f s 6 ? f s 1- lane 16- bit serialization 62.5 8 ? f s f s 16 ? f s 1- lane 14- bit serialization 71.4 7 ? f s f s 14 ? f s 1- lane 12- bit serialization 80 6 ? f s f s 12 ? f s 217314f
22 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information programmable lvds output current the default output driver current is 3.5ma . this current can be adjusted by control register a2 in t he serial pro - gramming mode. available current levels are 1.75ma , 2.1ma , 2.5ma , 3ma , 3.5ma , 4ma and 4.5ma . in the par - allel programming mode, the sck pin can select either 3.5ma or 1.75ma . optional lvds driver internal termination in most cases, using just an external 100? termina - tion resistor will give excellent lvds signal integrity. in addition, an optional internal 100? te rmination resistor can be enabled by serially programming mode con - trol register a2 . the internal termination helps absorb any reflections caused by imperfect termination at the receiver. when the internal termination is enabled, the output driver current is doubled to maintain the same output voltage swing. in the parallel programming mode the sdo pin enables internal termination. internal termination should only be used with 1.75ma , 2.1 ma or 2.5ma lvds output current modes. data format table 2 shows the relationship between the analog input voltage and the digital data output bits. by default the output data format is offset binary. the 2 s complement format can be selected by serially programming mode control register a1 . digital output randomizer interference from the a/d digital outputs is sometimes unavoidable. digital interference may be from capacitive or inductive coupling or coupling through the ground plane. even a tiny coupling factor can cause unwanted tones in the adc output spectrum. by randomizing the digital output before it is transmitted off chip, these unwanted tones can be randomized which reduces the unwanted tone amplitude. the digital output is randomized by applying an exclusive- or logic operation between the lsb and all other data output bits. to decode, the reverse operation is applied an exclusive-or operation is applied between the lsb and all other bits. the fr and dco outputs are not affected. the output randomizer is enabled by serially programming mode control register a1 . table 2. output codes vs input voltage a in + C a in C ( 2 v r ange) d13 - d0 (offset binary) d 13 - d0 (2 s complement) > 1 .000000v + 0.999878v + 0.999756v 11 1111 1111 1111 11 1111 1111 1111 11 1111 1111 1110 01 1111 1111 1111 01 1111 1111 1111 01 1111 1111 1110 + 0.000122v + 0.000000v C 0.000122v C 0.000244v 10 0000 0000 0001 10 0000 0000 0000 01 1111 1111 1111 01 1111 1111 1110 00 0000 0000 0001 00 0000 0000 0000 11 1111 1111 1111 11 1111 1111 1110 C 0.999878v C 1.000000v 23 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information digital output test pattern to allow in-circuit testing of the digital interface to the a/d, there is a test mode that forces the a/d data out - puts ( d13 - d0 ) of all channels to known values. the digital output test patterns are enabled by serially programming mode control registers a3 and a4 . when enabled, the test patterns override all other formatting modes : 2 s comple - ment and randomizer. output disable the digital outputs may be disabled by serially program - ming mode control register a2 . t he current drive for all digital outputs including dco and fr are disabled to save power or enable in-circuit testing. when disabled the com - mon mode of each output pair becomes high impedance, but the differential impedance may remain low. sleep and nap modes the a/d may be placed in sleep or nap modes to con - serve power. in sleep mode the entire device is powered down, resulting in 2mw power consumption. sleep mode is enabled by mode control register a1 (serial program - ming mode), or by sdi (parallel programming mode). the time required to recover from sleep mode is about 2ms . in nap mode any combination of a/d channels can be powered down while the internal reference circuits and the pll stay active, allowing faster wake-up than from sleep mode. recovering from nap mode requires at least 100 clock cycles. if the application demands very accurate dc settling then an additional 50s should be allowed so the on-chip references can settle from the slight tem - perature shift caused by the change in supply current as the a/d leaves nap mode. nap mode is enabled by mode control register a1 in the serial programming mode. device programming modes the operating modes of the lt m2173 -14 can be pro - grammed by either a parallel interface or a simple serial interface. the serial interface has more flexibility and can program all available modes. the parallel interface is more limited and can only program some of the more commonly used modes. parallel programming mode to use the parallel programming mode, par/ ser should be tied to v dd . the cs , sck, sdi and sdo pins are binary logic inputs that set certain operating modes. these pins can be tied to v dd or ground, or driven by 1.8v , 2.5v , or 3.3v cmos logic. when used as an input, sdo should be driven through a 1k series resistor. table 3 shows the modes set by cs , sck, sdi and sdo. table 3. parallel programming mode control bits (par/ ser = v dd ) pin description cs 2- lane / 1- lane selection bit 0 = 2- lane, 16- bit serialization output mode 1 = 1- lane, 14- bit serialization output mode sck lvds current selection bit 0 = 3.5ma lvds current mode 1 = 1.75ma lvds current mode sdi power down control bit 0 = normal operation 1 = sleep mode sdo internal termination selection bit 0 = internal termination disabled 1 = internal termination enabled serial programming mode to use the serial programming mode, par/ ser should be tied to ground. the cs , sck, sdi and sdo pins become a serial interface that program the a/d mode control regis - ters. data is written to a register with a 16- bit serial word. data can also be read back from a register to verify its contents. 217314f
24 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information table 4. serial programming mode register map (par/ ser = gnd) register a0 : reset register (address 00h ) d7 d6 d5 d4 d3 d2 d1 d0 reset x x x x x x x bit 7 reset software reset bit 0 = not used 1 = software reset. all mode control registers are reset to 00h . t h e adc is momentarily placed in sleep mode. after the reset spi write command is complete, bit d7 i s a utomatically set back to zero. the reset register is write only. bits 6- 0 unused, don t care bits. register a1 : format and power-down register (address 01h ) d7 d6 d5 d4 d3 d2 d1 d0 dcsoff rand twoscomp sleep nap_4 n a p_ 3 n a p_ 2 n a p_1 bit 7 dcsoff clock duty cycle stabilizer bit 0 = clock duty cycle stabilizer on 1 = clock duty cycle stabilizer off. this is not recommended. b i t 6 rand data output randomizer mode control bit 0 = data output randomizer mode off 1 = data output randomizer mode on b i t 5 twoscomp two s complement mode control bit 0 = offset binary data format 1 = two s c omplement data format b its 4- 0 sleep : nap_x sleep/nap mode control bits 00000 = normal operation 0xxx1 = channel 1 in nap mode 0xx1x = channel 2 in nap mode 0x1xx = channel 3 in nap mode 01xxx = channel 4 in nap mode 1xxxx = sleep mode. channels 1, 2, 3 and 4 are disabled note : any combination of channels can be placed in nap mode. serial data transfer starts when cs is taken low. the data on the sdi pin is latched at the first 16 rising edges of sck. any sck rising edges after the first 16 are ignored. the data transfer ends when cs is taken hi gh again. the first bit of the 16- bit input word is the r/ w bit. the next seven bits are the address of the register ( a6 : a0 ). the final eight bits are the register data ( d7 : d0 ). if the r/ w bit is low, the serial data ( d7 : d0 ) will be writ - ten to the register set by the address bits ( a6 : a0 ) . if the r/ w bit is high, data in the register set by the address bits ( a6 : a0 ) will be read back on the sdo pin (see the timing diagrams section). during a read back command the register is not updated and data on sdi is ignored. the sdo pin is an open-drain output that pulls to ground with a 200? impedance. if register data is read back through sdo, an external 2k pull-up resistor is required. if serial data is only written and read back is not needed, then sdo can be left floating and no pull-up resistor is needed. table 4 shows a map of the mode control?registers. 217314f
25 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information register a2 : output mode register (address 02h ) d7 d6 d5 d4 d3 d2 d1 d0 ilvd s2 ilvd s1 ilvd s0 termon outoff outmode2 outmo de1 outmode0 bits 7- 5 ilvd s2 : ilvd s0 lvds output current bits 000 = 3.5ma l v ds output driver current 001 = 4.0ma lv ds output driver current 010 = 4.5ma lv ds output driver current 011 = not used 100 = 3.0ma lv ds output driver current 101 = 2.5ma lv ds output driver current 110 = 2.1ma lv ds output driver current 111 = 1.75ma lv ds output driver current bit 4 termon lvds internal termination bit 0 = internal termination off 1 = internal termination on. lvds output driver current is 2x t h e current set by ilvd s2 : ilvd s0 . internal termination should only be used with 1.75ma , 2.1ma or 2.5ma lvds output current modes. bit 3 outoff output disable bit 0 = digital outputs are enabled. 1 = digital outputs are disabled. b i ts 2- 0 outmo de2 : outmo de0 digital output mode control bits 000 = 2- l anes, 16- b it serialization 001 = 2- lanes, 14- b it serialization 010 = 2- lanes, 12- b it serialization 011 = not used 100 = not used 101 = 1- lane, 14- b it serialization 110 = 1- lane, 12- b it serialization 111 = 1- lane, 16- b it serialization register a3 : test pattern msb register (address 03h ) d7 d6 d5 d4 d3 d2 d1 d0 outtest x tp13 tp12 tp11 tp10 tp9 tp8 bit 7 outtest digital output test pattern control bit 0 = digital output test pattern off 1 = digital output test pattern on b i t 6 unused, don t care bit. bit 5- 0 tp13 : tp8 test pattern data bits (msb) tp13 : t p8 s et the test pattern for data bit 13 (msb) through data bit 8. register a4 : test pattern lsb register (address 04h ) d7 d6 d5 d4 d3 d2 d1 d0 tp7 tp6 tp5 tp4 tp3 tp2 tp1 tp0 bit 7- 0 tp7 : tp0 test pattern data bits (lsb) tp7 : tp 0 s et the test pattern for data bit 7 through data bit 0 (lsb). 217314f
26 for more information www.linear.com/LTM2173-14 lt m2173 -14 applications information software reset if serial programming is used, the mode control regis - ters should be programmed as soon as possible after the power supplies turn on and are stable. the first serial command must be a software reset which will reset all register data bits to logic 0. to perform a software reset, bit d7 in the reset register is written with a logic 1. after the reset spi write command is complete, bit d7 is auto - matically set back to zero. gro unding and bypassing the lt m2173 -14 requires a printed circuit board with a clean unbroken ground plane. a multilayer board with an internal ground plane in the first layer beneath the adc is recommended. layout for the printed circuit board should ensure that digital and analog signal lines are separated as much as possible. in particular, care should be taken not to run any digital track alongside an analog signal track or underneath the adc. bypass capacitors are integrated inside the package ; addi - tional capacitance is optional. the analog inputs, encode signals, and digital outputs should not be routed next to each other. ground fill and grounded vias should be used as barriers to isolate these signals from each other. the pin assignments of the lt m2173 -14 allow a flow-through layout that makes it possible to use multiple parts in a small area when a large num - ber of adc channels are required. the lt m2 173 module has similar layout rules to other bga pack- ages. the layout can be implemented with 6mil blind vias and 5mil traces. the pinout has been designed to minimize the space required to route the analog and digital traces. the analog and digital traces can essen - tially be routed within the width of the package. this allows multiple packages to be located close together for high channel count applications. trace lengths for the analog inputs and digital outputs should be matched as well as possible. table 5 lists the trace lengths for the analog inputs and digital outputs inside the package from the die pad to the package pad. these should be added to the pcb trace lengths for best matching. the material used for the substrate is bt (bismaleimide- triazine), supplied by mitsubishi gas and chemical. in the dc to 125mhz range, the speed for the analog input sig - nals is 198ps /i n or 7.7 9 5 p s /mm. the speed for the digital outputs is 188.5ps/in or 7.417p s /mm. heat transfer most of the heat generated by the lt m2173 -14 is trans - ferred from the die through the bottom of the package onto the printed circuit board. the ground pins should be connected to the internal ground planes by multiple vias. table 5. internal trace lengths pin name length (mm) e7 ou t1a C 1.775 e8 out1a + 1.947 c8 out1b C 1.847 d8 out1b + 1.850 c9 out2a C 3.199 c10 out2a + 3.196 f7 out2b C 0.706 f8 out2b + 0.639 j7 out3a + 0.436 table 5. internal trace lengths pin name length (mm) k8 out 3b C 0.379 k7 out3b + 0.528 l8 out4a C 1.862 m8 out4a + 1.847 m10 out4b C 4.021 m9 out4b + 4.016 b1 a i n1 C 4.689 b2 a i n1 + 4.709 g1 a i n2 C 3.376 table 5. internal trace lengths pin name length (mm) g2 a i n2 + 3.372 h2 a i n3 C 3.301 h1 a i n3 + 3.346 n2 a i n4 C 4.726 n1 a i n4 + 4.691 p6 enc C 4.106 p5 enc + 4.106 l5 cs 0.919 g8 dco C 1.157 table 5. internal trace lengths pin name length (mm) g7 dco + 1.088 h7 fr C 1.117 h8 fr + 1.038 a7 par/ser 3.838 l6 sck 0.240 e6 sdo 0.453 m6 sdi 1.069 b3 v c m12 3.914 n3 v c m34 3.915 217314f
27 for more information www.linear.com/LTM2173-14 lt m2173 -14 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or patent rights of analog devices. package description notes: 1. dimensioning and tolerancing per asme y14.5m-1994 2. all dimensions are in millimeters ball designation per jesd ms-028 and jep95 4 3 details of pin #1 identifier are optional, but must be located within the zone indicated. the pin #1 identifier may be either a mold or marked feature package top view x aaa z 3 see notes bga 140 1116 rev c tray pin 1 bevel package in tray loading orientation component pin ?a1? ?b (140 places) d detail b package side view m x yzddd m zeee 0.4 ? 140x y aaa z e e a2 f e g ltmxxxxxx module detail a suggested pcb layout top view 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 5.200 4.400 4.400 5.200 3.600 2.800 2.000 1.200 0.400 0.000 0.400 1.200 2.000 2.800 3.600 4 pin ?a1? corner 1 p detail a c d e f g h j k l m n a b 10 9 8 7 6 5 4 3 2 pin 1 package bottom view b b a z bga package 140-lead (11.25mm 9.00mm 2.72mm) (reference ltc dwg # 05-08-1849 rev c) 7 see notes 5. primary datum -z- is seating plane 6. solder ball composition can be 96.5% sn/3.0% ag/0.5% cu or sn pb eutectic 7 package row and column labeling may vary among module products. review each package layout carefully ! symbol a a1 a2 b b1 d e e f g h1 h2 aaa bbb ccc ddd eee min 2.57 0.35 2.22 0.45 0.37 0.27 1.95 nom 2.72 0.40 2.32 0.50 0.40 11.25 9.0 0.80 10.40 7.2 0.32 2.00 max 2.87 0.45 2.42 0.55 0.43 0.37 2.05 0.15 0.10 0.12 0.15 0.08 total number of balls: 140 dimensions notes ball ht ball dimension pad dimension substrate thk mold cap ht detail b substrate a1 ccc z // bbb z z h2 h1 b1 mold cap please refer to http : //www.linear.com/product/ lt m2173 -14#packaging for the most recent package drawings. 217314f
28 for more information www.linear.com/LTM2173-14 lt m2173 -14 lt 0318 ? printed in usa www.linear.com/ltc2173-14 ? analog devices, inc. 2018 related parts part number description comments adcs ltc2170-14/ltc2171-14/ ltc2172-14 14-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw /234mw/360mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2170-12/ltc2171-12/ ltc2172-12 12-bit, 25msps/40msps/65msps 1.8v quad adcs, ultralow power 178mw /234mw/360mw, 70.5db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-12/ltc2174-12/ ltc2175-12 12-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 412mw /481mw/567mw, 70.5db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 ltc2173-14/ltc2174-14/ ltc2175-14 14-bit, 80msps/105msps/125msps 1.8v quad adcs, ultralow power 412mw /481mw/567mw, 73.4db snr, 85db sfdr, serial lvds outputs, 7mm 8mm qfn-52 amplifiers/filters ltc6412 800mhz, 31db range, analog-controlled variable gain amplifier continuously adjustable gain control, 35dbm oip3 at 240mhz, 10db noise figure, 4mm 4mm qfn-24 ltc6420-20 1.8ghz dual low noise, low distortion differential adc drivers for 300mhz if fixed gain 10v/v, 1nv/ hz total input noise, 80ma supply current per amplifier, 3mm 4mm qfn-20 ltc6421-20 1.3ghz dual low noise, low distortion differential adc drivers fixed gain 10v/v, 1nv/hz total input noise, 40ma supply current per amplifier, 3mm 4mm qfn-20 ltc6605-7/ltc6605-10/ ltc6605-14 dual matched 7mhz/10mhz/14mhz filters with adc drivers dual matched 2nd order lowpass filters with differential drivers, pin-programmable gain, 6mm 3mm dfn-22 signal chain receivers lt m 90 02 14- bit dual channel if/baseband receiver subsystem integrated high speed adc, passive filters and fixed gain differential amplifiers typical application single-ended to differential conversion using lt c6409 and 50mhz lowpass filter (only one channel shown). filter for use at 92.16msps LTM2173-14 n3 h2 h1 g1 g2 b3 b1 b2 v cm12 a in2 + a in2 ? a in3 + a in3 ? v cm34 a in4 + a in4 ? a in1 + a in1 ? out1a + out1a ? dco + dco ? fr + fr ? n1 n2 h7 h8 g8 g7 e7 e8 enc + enc ? p5 p6 b6 c5 1.8v 1.8v sense v dd v ref ov dd 33pf 100pf 150pf 180nh 180nh 3.3v 180nh 180nh 150pf 150 474 37.4 37.4 out ? out + v ocm in + v + in ? 474 75 75 66.9 66.9 0.1f 0.8pf 0.8pf 68pf 68pf 0.1f 217314 ta03 ? + 150 shdn gnd 49.9 50 ??? ltc6409 217314f

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